1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a liquid crystal panel with TFTs and a photoelectric conversion apparatus.
2. Related Background Art
The size of a TFT panel is rapidly becoming large nowadays, under the circumstances of developments of manufacture techniques for TFT liquid crystal panels and wide applications of area sensors with photoelectric conversion elements such as X-ray image pickup apparatuses. Together with a trend of large size panels, a pattern pitch is also becoming fine and a panel manufacture yield is lowering. The reasons for this may be ascribed to the following.
(1) As the size of a panel becomes large, a wiring distance per panel elongates and a wiring disconnection probability rises.
(2) As the pattern pitch becomes fine, the number of TFTs per panel and the area of wiring cross points per panel increases and a short circuit probability rises.
(3) Occurrence of electrostatic defects (ESD). As the size of a panel becomes large, a contact area with the panel increases so that the amount of static electricity to be caused by friction or peel-off increases and quick and uniform discharge of electricity is becoming more difficult. As the pattern pitch becomes fine, the number of pattern cross points increases and the probability of defective panels to be caused by ESD rises.
Of these reasons, the reason (3) of ESD can be effectively alleviated by connecting the common electrode bias line and gate lines, or the common electrode bias line and gate and transfer lines, to a metal line to maintain these lines at the same potential. However, these connected lines are required to be separated at an intermediate process of manufacturing a semiconductor device with a TFT panel. For example, this separation can be performed by a panel slicing process which uses a blade made of diamond grains solidified with resin. Since the metal lines are cut, some reliability problem may occur such as abnormal wiring to be caused by metal particles or chips, short circuit of metal lines to be caused by metal expansion, metal fatigue and corrosion to be caused by water or heat during the slicing.
It is an object of the present invention to provide a semiconductor device with a TFT matrix panel which can effectively prevent ESD during manufacture processes and improve a manufacture yield.
It is another object of the present invention to provide a semiconductor device which can omit a separation process to be executed by the slicing process by inserting a resistor having a desired resistance value between respective wiring lines, i.e., by interconnecting the lines by the resistor having a desired resistance value, and even if the separation process is necessary, it can be performed in the area where a metal wiring line is not formed.
It is another object of the present invention to provide a semiconductor device which can solve the problem associated with the separation process to be executed by the slicing process in the metal conductor to avoid ESD.
It is another object of the present invention to provide a semiconductor device with a TFT matrix panel which can maintain the effects of preventing ESD until the panel is finally mounted on an apparatus, by electrically connecting wiring lines by resistors.
It is another object of the present invention to provide a semiconductor device having a plurality of thin film transistors and capacitors disposed on a substrate, wherein: a first electrode of each of the plurality of capacitors is connected to one of a source and a drain of each of the plurality of thin film transistors; a second electrode of each of the plurality of capacitors is connected to a common electrode bias line; a gate of each of the plurality of thin film transistors is connected to a corresponding one of a plurality of gate lines; the other of the source and the drain of each of the plurality of thin film transistors is connected to a corresponding one of a plurality of transfer lines; and the common electrode bias line, the plurality of gate lines and the plurality of transfer lines are electrically connected.
It is another object of the present invention to provide a semiconductor device having a plurality of thin film transistors and capacitors disposed on a substrate, wherein: a first electrode of each of the plurality of capacitors is connected to one of a source and a drain of each of the plurality of thin film transistors; a second electrode of each of the plurality of capacitors is connected to common electrode bias lines; a gate of each of the plurality of thin film transistors is connected to a corresponding one of a plurality of gate lines; and the common electrode bias lines and the plurality of gate lines are electrically connected.
It is another object of the present invention to provide a semiconductor device having a plurality of thin film transistors and associated wiring lines formed on a substrate, wherein the wiring lines are disposed vertically and horizontally crossing each other, the wiring lines are electrically insulated at each cross point and the wiring lines are connected via resistors.
According to the semiconductor device of the invention, the common electrode bias line and the plurality of gate lines are electrically connected, or the common electrode bias line, the plurality of gate lines and the plurality of transfer lines are electrically connected. Since the common electrode bias line and the plurality of gate lines, or the common electrode bias line, the plurality of gate lines and the plurality of transfer lines are electrically connected, they can be maintained at the same potential. Therefore, ESD of each line connected, to be caused by static electricity during panel manufacture, can be prevented and a manufacture yield can be improved.
Also according to the semiconductor device of the invention, since lines are interconnected by the resistor having a desired resistance value, a slicing process is not necessarily required, and even if the slicing process is necessary, it can be performed along the semiconductor layer so that the above-described reliability problem can be solved.